---
title: "Analyzing CUDA Workloads Using a Detailed GPU Simulator"
description: "Modern GPUs offer far more raw compute than CPUs, yet many CUDA programs, even highly… 46 references, cited by 101 papers here."
authors: ["Ali Bakhoda", "George L. Yuan", "Wilson W. L. Fung", "Henry Wong", "Tor M. Aamodt"]
year: 2009
venue: "ISPASS 2009"
source: "https://doi.org/10.1109/ISPASS.2009.4919648"
doi: "10.1109/ispass.2009.4919648"
licence: "author copy (ubc.ca) — read only"
summary_licence: "Elamur Cosmic License"
canonical: "https://research.elamur.ai/free/en/papers/bakhoda-2009-analyzing-cuda-workloads-detailed-gpu/"
---
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# Analyzing CUDA Workloads Using a Detailed GPU Simulator

**Authors:** Ali Bakhoda, George L. Yuan, Wilson W. L. Fung, Henry Wong and [Tor M. Aamodt](https://md.research.elamur.ai/free/en/authors/tor-m-aamodt/) · **Year:** 2009 · **Venue:** ISPASS 2009 · **Licence:** author copy (ubc.ca) — read only

**Links:** [Publisher's page](https://doi.org/10.1109/ispass.2009.4919648) · [PDF](https://people.ece.ubc.ca/aamodt/papers/gpgpusim.ispass09.pdf) · [DOI 10.1109/ispass.2009.4919648](https://doi.org/10.1109/ispass.2009.4919648) · [OpenAlex](https://openalex.org/W1979527452)

**Citations:** 1,663 citations (OpenAlex, 2026-10-14) · [101](https://md.research.elamur.ai/free/en/papers/bakhoda-2009-analyzing-cuda-workloads-detailed-gpu/cited-by/) in our library, of the 149,439 papers whose bibliographies we read

## Summary
Modern GPUs offer far more raw compute than CPUs, yet many CUDA programs, even highly data-parallel ones, fall well short of peak throughput. To understand why, the authors built GPGPU-Sim, a detailed cycle-level simulator that executes NVIDIA's PTX virtual instruction set. They configured it to resemble high-end graphics cards of the time and ran twelve non-trivial CUDA applications on it. They deliberately chose programs with reported speedups under 50×, since those seem most in need of hardware or software improvements. The study varies interconnect topology, caching of global and local memory, the memory controller, CTA distribution across cores, and memory request coalescing. It also profiles instruction mix, warp branch divergence, and DRAM locality.

The main findings are:
- Performance depends more on interconnect bisection bandwidth than on latency.
- Caching memory that lacks locality can hurt performance.
- Running fewer concurrent CTAs than the hardware permits sometimes helps, because it reduces memory contention.

These results give architects and CUDA developers evidence-based guidance for designing manycore processors.

## Key points
- **Motivation from CUDA Zone listings (Feb 2009):** of 209 listed applications, 136 had performance claims. Of those, 52 claimed at least 50× speedup and 29 claimed at least 100×.
- **Baseline simulated core:**
  - SIMD width 8 with a 24-stage in-order pipeline.
  - 32-thread warps, each taking four cycles per instruction.
  - Immediate post-dominator reconvergence to handle branch divergence.
  - 16KB banked shared memory per core, plus per-core texture and constant caches.
- **Baseline memory system:** a 6x6 mesh interconnect links the cores to the memory controllers. Each controller drives two GDDR3 chips, and successive 2KB DRAM pages are spread across banks and chips.
- **Bandwidth beats latency:** halving interconnect bandwidth hurt performance more than raising per-router latency 5.3×, from 3 to 19 cycles.
- **Inter-warp coalescing:** it gave a 6.1% harmonic-mean speedup over intra-warp coalescing, and up to 41% for some applications. The highly tuned CUDA SDK benchmarks gained under 1%.

## Interesting ideas
- **Run real programs through a virtual ISA.** Simulating at the PTX level lets unmodified CUDA applications be studied under many hypothetical hardware configurations. Any field that wants to test design changes on real workloads, without building hardware, could use the same approach.
- **Pick workloads where results are mediocre.** Ignoring the headline 100× successes and studying modest-speedup applications points the analysis at the real bottlenecks. This is a useful way to choose benchmarks in any evaluation.
- **More parallelism is not always better.** Limiting concurrent CTAs below the resource maximum sometimes improved throughput by easing memory contention. This suggests that adaptive concurrency limits deserve attention in other shared-resource systems, such as batch schedulers or data pipelines.
- **Measure bandwidth and latency separately.** Varying the two independently showed which one actually limits performance. That clarity can justify cheaper, higher-latency designs, as with the mesh chosen here.
- **Merge redundant requests across groups.** Inter-warp coalescing removes duplicate memory requests for data-dependent access patterns. The idea of deduplicating fetches across concurrent workers could carry over to caching layers and data loaders.

*Our summary of the paper, in our own words — not its text. The work belongs to its authors; read it at the links above.*

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- [University of British Columbia](https://md.research.elamur.ai/free/en/universities/university-of-british-columbia/) — University, Vancouver, Canada · 104 works · 37,402 citations

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## Cite

Cite as: Ali Bakhoda, George L. Yuan, Wilson W. L. Fung, Henry Wong and Tor M. Aamodt. 2009. Analyzing CUDA Workloads Using a Detailed GPU Simulator. ISPASS 2009.

The paper itself, not this page. BibTeX from the library's record of the work.

```bibtex
@inproceedings{bakhoda2009analyzing,
  title = {{Analyzing CUDA Workloads Using a Detailed GPU Simulator}},
  author = {Ali Bakhoda, George L. Yuan, Wilson W. L. Fung, Henry Wong and Tor M. Aamodt},
  booktitle = {ISPASS 2009},
  year = {2009},
  doi = {10.1109/ispass.2009.4919648},
  url = {https://doi.org/10.1109/ispass.2009.4919648}
}
```

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*Updated 2 November 2026*