---
title: "VerilogLAVD — paper by Long et al. (2026) — summary and ideas"
description: "LLMs often miss security flaws in Verilog RTL because HDL code runs concurrently. 24 references."
authors: ["Xiang Long", "Yingjie Xia", "Li Kuang", "Yao Wan", "ZiHao Liu"]
year: 2026
venue: "Proceedings of the 64th Annual Meeting of the Association for Computational Linguistics (Volume 1: Long Papers)"
source: "https://aclanthology.org/2026.acl-long.1304/"
doi: "10.18653/v1/2026.acl-long.1304"
licence: "CC BY 4.0 (ACL Anthology)"
licence_url: "https://creativecommons.org/licenses/by/4.0/"
summary_licence: "Elamur Cosmic License"
canonical: "https://research.elamur.ai/free/en/papers/long-2026-veriloglavd-llm-aided-pattern-generation/"
---
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# VerilogLAVD: LLM-Aided Pattern Generation for Verilog CWE Detection

**Authors:** [Xiang Long](https://md.research.elamur.ai/free/en/authors/xiang-long/), Yingjie Xia, Li Kuang, [Yao Wan](https://md.research.elamur.ai/free/en/authors/yao-wan/) and ZiHao Liu · **Year:** 2026 · **Venue:** [Proceedings of the 64th Annual Meeting of the Association for Computational Linguistics (Volume 1: Long Papers)](https://md.research.elamur.ai/free/en/venues/acl/) ([ACL 2026](https://md.research.elamur.ai/free/en/venues/acl/2026/)) · **Publisher:** [Association for Computational Linguistics](https://md.research.elamur.ai/free/en/publishers/association-for-computational-linguistics/) · **Licence:** [CC BY 4.0 (ACL Anthology)](https://creativecommons.org/licenses/by/4.0/)

**Links:** [Publisher's page](https://aclanthology.org/2026.acl-long.1304/) · [PDF](https://aclanthology.org/2026.acl-long.1304.pdf) · [DOI 10.18653/v1/2026.acl-long.1304](https://doi.org/10.18653/v1/2026.acl-long.1304) · [OpenAlex](https://openalex.org/W7166887504)

**Citations:** 0 citations (OpenAlex, 2026-10-14)

## Summary
LLMs often miss security flaws in Verilog RTL because HDL code runs concurrently. A hardware vulnerability usually comes from several statements interacting in parallel rather than from one sequential path, so models that read raw code or flattened graphs tend to overlook it. VerilogLAVD changes the LLM's role. Instead of judging code directly, the model converts a CWE description into an executable Traversal Detection Pattern (TDP): a JSON-like rule built from traversal primitives, parameters and filters. TDPs run on VeriPG, a property graph that merges AST, CFG and DDG by aligning shared AST node identifiers. In VeriPG, parallel statements hang under a common CFG parent, and DDG edges from non-blocking assignments are pruned to reflect true signal timing. A Validator treats graph traversal as FSM state transitions, rejects illegal steps and returns errors to the LLM for repair. Running the validated TDPs yields deterministic verdicts with line locations. The method beats pure-LLM and RAG baselines and uncovered real bugs in open-source hardware repositories, offering a practical neuro-symbolic path to early-stage RTL security checks.

## Key points
- F1 rises by 133% relative to LLM-based detection. The absolute gains are 0.31 over pure-LLM baselines and 0.25 over RAG baselines.
- VeriPG is a directed property graph with AST, CFG and DDG edge types. It explicitly distinguishes blocking (`=`) from non-blocking (`<=`) assignments, which matters for cases such as CWE-1280.
- On open-source designs, CWE-1245 (improper FSM transitions) reached 66.1% strict precision (39/59 true positives).
  - For CWE-1280, including actionable "Indeterminate" warnings, such as the e203 chip's absent local resets, produces a 69.2% useful detection rate.
  - CWE-1271 (uninitialized values) produced many false positives (2/20 true positives).
- Stated limitations include the cost of building VeriPG for full-chip designs (evaluation is module- and subsystem-level), LLM context limits, and output non-determinism.
- Code and datasets are released at github.com/Chip-Security-Lab/VerilogLAVD.

*Our summary of the paper, in our own words — not its text. The work belongs to its authors; read it at the links above.*

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- [Zhejiang University](https://md.research.elamur.ai/free/en/universities/zhejiang-university/) — University, Hangzhou, China · 172 works · 12,988 citations
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- [Central South University](https://md.research.elamur.ai/free/en/universities/central-south-university/) — University, Changsha, China · 15 works · 582 citations
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## Cite

Cite as: Xiang Long, Yingjie Xia, Li Kuang, Yao Wan and ZiHao Liu. 2026. VerilogLAVD: LLM-Aided Pattern Generation for Verilog CWE Detection. Proceedings of the 64th Annual Meeting of the Association for Computational Linguistics (Volume 1: Long Papers).

The paper itself, not this page. BibTeX from the library's record of the work.

```bibtex
@inproceedings{long2026veriloglavd,
  title = {{VerilogLAVD: LLM-Aided Pattern Generation for Verilog CWE Detection}},
  author = {Xiang Long, Yingjie Xia, Li Kuang, Yao Wan and ZiHao Liu},
  booktitle = {Proceedings of the 64th Annual Meeting of the Association for Computational Linguistics (Volume 1: Long Papers)},
  year = {2026},
  doi = {10.18653/v1/2026.acl-long.1304},
  url = {https://doi.org/10.18653/v1/2026.acl-long.1304}
}
```

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*Updated 1 November 2026*