---
title: "NVIDIA Tesla V100 GPU Architecture — paper by NVIDIA (2017)"
description: "This NVIDIA whitepaper presents the Tesla V100 accelerator and its Volta GV100 GPU, the successor to Pascal… Cited by 125 papers here."
authors: ["NVIDIA"]
year: 2017
venue: "NVIDIA whitepaper"
source: "https://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf"
licence: "NVIDIA, free download — read only"
summary_licence: "Elamur Cosmic License"
canonical: "https://research.elamur.ai/free/en/papers/nvidia-2017-nvidia-tesla-v100-gpu-architecture/"
---
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# NVIDIA Tesla V100 GPU Architecture

**Authors:** [NVIDIA](https://md.research.elamur.ai/free/en/authors/nvidia/) · **Year:** 2017 · **Venue:** NVIDIA whitepaper · **Licence:** NVIDIA, free download — read only

**Links:** [Publisher's page](https://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf) · [PDF](https://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf)

**Citations:** [125](https://md.research.elamur.ai/free/en/papers/nvidia-2017-nvidia-tesla-v100-gpu-architecture/cited-by/) in our library, of the 149,439 papers whose bibliographies we read

## Summary
This NVIDIA whitepaper presents the Tesla V100 accelerator and its Volta GV100 GPU, the successor to Pascal GP100. It targets data center workloads in deep learning and HPC, where compute throughput, memory bandwidth, and multi-GPU scaling are the main bottlenecks. The document is a vendor architecture description, not an experimental study. It covers a redesigned Streaming Multiprocessor (SM), new Tensor Cores for mixed-precision matrix math, a merged L1 cache and shared memory, second-generation NVLink, a faster HBM2 memory subsystem, and programming-model changes such as independent thread scheduling, a hardware-accelerated Multi-Process Service (MPS), and Cooperative Groups. According to NVIDIA, the new SM uses energy 50% more efficiently than Pascal, and Tensor Cores raise peak deep learning throughput by up to 12x for training and 6x for inference. Memory and interconnect bandwidth also grow substantially. The architecture matters because it made specialized matrix units and mixed precision the standard hardware basis for training large neural models.

## Key points
- GV100 has 21.1 billion transistors on an 815 mm² die. It is built on a TSMC 12 nm FFN process customized for NVIDIA, and the full chip contains 84 SM units.
- Tensor Cores perform a 4x4 matrix multiply-accumulate on FP16 inputs with FP32 accumulation. According to NVIDIA, they lift peak TFLOPS by as much as 12x for training and 6x for inference relative to Pascal.
- Second-generation NVLink provides up to 6 links and 300 GB/s in total, versus 4 links and 160 GB/s on GP100. It also adds CPU mastering and cache coherence with IBM Power 9 servers.
- The 16 GB of Samsung HBM2 memory peaks at 900 GB/s. Together with a new memory controller, it delivers about 1.5x the usable bandwidth of GP100 and reaches up to 95% utilization on many workloads.
- At the system level, a DGX-1 with V100 is reported to train up to 3x faster than an eight-way GP100 server. The DGX Station is presented as a personal deep learning workstation.

## Interesting ideas
- **Mixed precision as a design principle.** Products are computed from low-precision FP16 inputs, while sums are accumulated in FP32. This keeps most of the speed and memory savings without losing numerical stability, and the same approach is now common in model training and quantized inference.
- **Separate integer and floating-point pipelines.** Volta can run address or index arithmetic at the same time as FP math, so bookkeeping no longer delays the main computation. Any pipeline that mixes control work with heavy numerics can benefit from overlapping the two.
- **Per-thread scheduling inside a warp.** Each thread gets its own program counter and call stack, with explicit synchronization used to reconverge. This makes fine-grained locking safe and allows starvation-free algorithms such as a doubly linked list with per-node locks. Giving up implicit lockstep for explicit sync points trades a little simplicity for correctness on irregular workloads.
- **Hardware support for sharing one accelerator.** Pascal ran MPS in software, while Volta does it in hardware. This lets many small jobs, typically inference requests, run on one GPU with better isolation and utilization, which is useful when serving many lightweight models.
- **Interconnect topology as part of the design.** DGX-1 links its GPUs in a hybrid cube mesh via NVLink. This shows that how devices are wired together can limit scaling as much as raw chip speed, a point worth weighing when planning multi-GPU training clusters.

*Our summary of the paper, in our own words — not its text. The work belongs to its authors; read it at the links above.*

📚 Shelves (1): [🖥️ Computer Science](https://md.research.elamur.ai/free/en/shelves/computer-science/) · 18,614 works

🧭 Topics (1): [⚡ GPU & parallel computing](https://md.research.elamur.ai/free/en/topics/gpu-parallel-computing/) · 41 works

## Cite

Cite as: NVIDIA. 2017. NVIDIA Tesla V100 GPU Architecture. NVIDIA whitepaper.

The paper itself, not this page. BibTeX from the library's record of the work.

```bibtex
@inproceedings{nvidia2017nvidia,
  title = {{NVIDIA Tesla V100 GPU Architecture}},
  author = {NVIDIA},
  booktitle = {NVIDIA whitepaper},
  year = {2017},
  url = {https://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf}
}
```

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