---
title: "Roofline — paper by Williams et al. (2009) — summary and ideas"
description: "Multicore chips are diverging in design: many simple cores versus a few complex ones… 30 references, cited by 332 papers here."
authors: ["Samuel Williams", "Andrew Waterman", "David Patterson"]
year: 2009
venue: "Communications of the ACM 52(4)"
source: "https://doi.org/10.1145/1498765.1498785"
doi: "10.1145/1498765.1498785"
licence: "author copy (berkeley.edu) — read only"
summary_licence: "Elamur Cosmic License"
canonical: "https://research.elamur.ai/free/en/papers/williams-2009-roofline-insightful-visual-performance-model/"
---
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# Roofline: An Insightful Visual Performance Model for Multicore Architectures

**Authors:** Samuel Williams, Andrew Waterman and [David Patterson](https://md.research.elamur.ai/free/en/authors/david-patterson/) · **Year:** 2009 · **Venue:** [Communications of the ACM 52(4)](https://md.research.elamur.ai/free/en/venues/communications-of-the-acm/) ([Communications of the ACM 2009](https://md.research.elamur.ai/free/en/venues/communications-of-the-acm/2009/)) · **Publisher:** [Association for Computing Machinery](https://md.research.elamur.ai/free/en/publishers/association-for-computing-machinery/) · **Licence:** author copy (berkeley.edu) — read only

**Links:** [Publisher's page](https://doi.org/10.1145/1498765.1498785) · [PDF](https://people.eecs.berkeley.edu/~kubitron/cs252/handouts/papers/RooflineVyNoYellow.pdf) · [DOI 10.1145/1498765.1498785](https://doi.org/10.1145/1498765.1498785) · [OpenAlex](https://openalex.org/W2002555321)

**Citations:** 2,456 citations (OpenAlex, 2026-10-14) · [332](https://md.research.elamur.ai/free/en/papers/williams-2009-roofline-insightful-visual-performance-model/cited-by/) in our library, of the 149,439 papers whose bibliographies we read

## Summary
Multicore chips are diverging in design: many simple cores versus a few complex ones, multithreading, and local stores in place of caches. This makes it harder for programmers, compiler writers and architects to reason about performance. The authors propose Roofline, a bound-and-bottleneck model that aims to give insight rather than exact predictions. It uses a log-log chart that plots attainable floating-point throughput against operational intensity, defined as flops per byte of DRAM traffic after the cache hierarchy has filtered accesses.

A kernel's speed is capped by whichever is lower: peak compute, or sustainable memory bandwidth multiplied by intensity. This produces a flat roof and a slanted roof that meet at a "ridge point". Bandwidth comes from the authors' own optimized microbenchmarks, not from DRAM pin specifications.

The model is then extended with "ceilings", which show the limit reached when a specific optimization is missing. These indicate which optimizations to apply and in what order. The approach is demonstrated on four diverse multicore machines (AMD Opteron X4, Intel Xeon Clovertown, IBM Cell, Sun UltraSPARC T2+) using floating-point kernels such as sparse matrix, stencil/structured grid and FFT codes. One chart per machine can be reused for any kernel.

## Key points
- Core bound: attainable GFlops/s = min(peak FP performance, peak memory bandwidth × operational intensity). Both lines are measured once per computer, not once per kernel.
- The dual-socket 2.2 GHz AMD Opteron X2 (model 2214) has a peak of 17.6 GFlops/s and 15 GB/s of measured sustainable bandwidth, which puts its ridge point at about 1 flop/byte.
- The Opteron X4 uses the same socket and therefore has the same DRAM bandwidth, but its peak compute is roughly 4× higher. Its ridge point moves to 4.4, so kernels need higher intensity to gain anything from it.
- Opteron X2 compute ceilings: 8.8 GFlops/s with an unbalanced add/multiply mix, and 2.2 GFlops/s when ILP/SIMD optimizations are also missing.
- Opteron X2 memory ceilings: 11 GB/s without software prefetching, 4.8 GB/s without NUMA memory affinity as well, and 2.7 GB/s with only unit-stride optimization.

## Interesting ideas
- **Aim for insight over accuracy.** The authors deliberately build an imperfect but intuitive model, as the 3Cs cache model did. Simple bounding charts can guide decisions better than precise but opaque predictors, for example when explaining throughput of NLP inference or data pipelines.
- **Measure traffic at the real bottleneck.** Counting bytes between caches and DRAM, rather than between CPU and cache, lets memory optimizations show up in the model. More generally, define the ratio at whichever interface actually limits throughput, such as disk, network or GPU memory.
- **Treat ceilings as an ordered optimization checklist.** Each missing optimization lowers the reachable limit, and the kernel's intensity indicates which group of fixes (compute or memory) matters. This turns profiling into a prioritized to-do list.
- **Use the ridge point as a one-number difficulty score.** Its x-coordinate summarizes how hard it is to reach a machine's peak, which helps compare hardware for a given workload before writing any code.
- **Use measured, sustainable limits rather than spec-sheet numbers.** Benchmarking achievable bandwidth gives honest roofs. The authors also suggest the model can extend to non-arithmetic operations, which makes it reusable outside floating-point work.

*Our summary of the paper, in our own words — not its text. The work belongs to its authors; read it at the links above.*

## Institutions

- [University of California, Berkeley](https://md.research.elamur.ai/free/en/universities/university-of-california-berkeley/) — University, Berkeley, United States · 209 works · 244,782 citations
- [Lawrence Berkeley National Laboratory](https://md.research.elamur.ai/free/en/labs/lawrence-berkeley-national-laboratory/) — Research institute, Berkeley, United States · 4 works · 41,948 citations

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## Cite

Cite as: Samuel Williams, Andrew Waterman and David Patterson. 2009. Roofline: An Insightful Visual Performance Model for Multicore Architectures. Communications of the ACM 52(4).

The paper itself, not this page. BibTeX from the library's record of the work.

```bibtex
@inproceedings{williams2009roofline,
  title = {{Roofline: An Insightful Visual Performance Model for Multicore Architectures}},
  author = {Samuel Williams, Andrew Waterman and David Patterson},
  booktitle = {Communications of the ACM 52(4)},
  year = {2009},
  doi = {10.1145/1498765.1498785},
  url = {https://doi.org/10.1145/1498765.1498785}
}
```

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*Updated 2 November 2026*